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NB7L11M 2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination
Description
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16 1
The NB7L11M is a differential 1-to-2 clock/data distribution chip with internal source termination and CML output structure, optimized for low skew and minimal jitter. The device is functionally equivalent to the EP11, LVEP11, or SG11 devices. Device produces two identical output copies of clock or data operating up to 8 GHz or 12 Gb/s, respectively. As such, NB7L11M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications. Inputs incorporate internal 50 W termination resistors and accept LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 6). Differential 16 mA CML output provides matching internal 50 W terminations, and 400 mV output swings when externally terminated, 50 W to VCC (See Figure 14). The device is offered in a low profile 3x3 mm 16-pin QFN package. Application notes, models, and support documentation are available at www.onsemi.com.
Features
QFN-16 MN SUFFIX CASE 485G
NB7L 11M ALYWG G
A L Y W G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
(Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
* * * * * * * * * * * *
Maximum Input Clock Frequency up to 8 GHz Typical Maximum Input Data Rate up to 12 Gb/s Typical < 0.5 ps of RMS Clock Jitter < 10 ps of Data Dependent Jitter 30 ps Typical Rise and Fall Times 110 ps Typical Propagation Delay 3 ps Typical Within Device Skew Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V CML Output Level (400 mV Peak-to-Peak Output) Differential Output Only 50 W Internal Input and Output Termination Resistors Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP and SG Devices Pb-Free Packages are Available*
VTCLK 50 W CLK CLK 50 W VTCLK Q1 Q0 Q0
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Figure 1. Logic Diagram
Q1
(c) Semiconductor Components Industries, LLC, 2006
January, 2006 - Rev. 1
1
Publication Order Number: NB7L11M/D
NB7L11M
VCC 16 VTCLK CLK CLK VTCLK 1 2 NB7L11M 3 4 5 VCC 6 Q1 7 Q1 8 VCC 10 9 Q0 15 Q0 14 VCC 13 12 11 VEE VEE VEE VEE Exposed Pad (EP)
Figure 2. QFN-16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin 1 2 Name VTCLK CLK I/O - LVPECL, CML, LVCMOS, LVTTL, LVDS LVPECL, CML, LVCMOS, LVTTL, LVDS - - CML Output CML Output - CML Output CML Output - Description Internal 50 W Termination Pin for CLK Inverted Differential Clock/Data Input. (Note 1)
3
CLK
Noninverted Differential Clock/Data Input. (Note 1)
4 5,8,13,16 6 7 9,10,11,12 14 15 -
VTCLK VCC Q1 Q1 VEE Q0 Q0 EP
Internal 50 W Termination Pin for CLK Positive Supply Voltage. All VCC pins must be externally connected to a Power Supply to guarantee proper operation. Inverted CLK output 1 with internal 50 W source termination resistor. (Note 2) Noninverted CLK output 1 with internal 50 W source termination resistor. (Note 2) Negative Supply Voltage. All VEE pins must be externally connected to a Power Supply to guarantee proper operation. Inverted CLK output 0 with internal 50 W source termination resistor. (Note 2) Noninverted CLK output 0 with internal 50 W source termination resistor. (Note 2) Exposed Pad. The thermally exposed pad on package bottom (see case drawing) must be attached to a heatsinking conduit. It is recommended to connect the EP to the lower potential (VEE).
1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage or left open, and if no signal is applied on CLK and CLK then the device will be susceptible to self-oscillation. 2. CML outputs require 50 W receiver termination resistor to VCC for proper operation.
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NB7L11M
Table 2. ATTRIBUTES
Characteristics ESD Protection Human Body Model Machine Model Charged Device Model Pb Pkg QFN-16 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 Level 1 Value > 1500 V > 50 V > 500 V Pb-Free Pkg Level 1
Moisture Sensitivity (Note 3)
UL 94 V-0 @ 0.125 in 285
Table 3. MAXIMUM RATINGS
Symbol VCC VI VINPP IIN Iout TA Tstg qJA qJC Tsol Parameter Positive Power Supply Input Voltage Differential Input Voltage |CLK - CLK| Input Current Through RT (50 W Resistor) Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 4) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm 2S2P (Note 4) QFN-16 QFN-16 QFN-16 Condition 1 VEE = 0 V VEE = 0 V VCC - VEE w 2.8 V VCC - VEE < 2.8 V Static Surge Continuous Surge QFN-16 VEE v VI v VCC Condition 2 Rating 3.6 3.6 2.8 |VCC - VEE| 45 80 25 50 -40 to +85 -65 to +150 42 36 3 to 4 265 265 Unit V V V mA mA mA mA C C C/W C/W C/W C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power).
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NB7L11M
Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs (VCC = 2.375 V to 3.465 V, VEE = 0 V, TA = -40C to +85C)
Symbol ICC VOH VOL Vth VIH VIL VIHCLK VILCLK VCMR VID IIH IIL RTIN RTOUT RTemp Coef Characteristic Power Supply Current (Input and Outputs open) Output HIGH Voltage (Note 6) Output LOW Voltage (Note 6) VCC - 60 VCC - 530 1125 Vth + 75 VEE 1200 VEE 1163 75 0 -10 45 45 25 0 50 50 6.38 Min Typ 85 VCC - 20 VCC - 420 Max 105 VCC VCC - 360 VCC - 75 VCC Vth - 75 VCC VCC - 75 VCC - 38 2500 100 10 55 55 Unit mA mV mV
(Note 5)
Differential Input Driven Single-Ended (see Figures 10 & 12) (Note 8) Input Threshold Reference Voltage Range (Note 7) Single-ended Input HIGH Voltage (Note 8) Single-ended Input LOW Voltage (Note 8) mV mV mV
Differential Inputs Driven Differentially (see Figures 11 & 13) (Note 8) Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Configuration) Differential Input Voltage (VIHCLK - VILCLK) Input HIGH Current Input LOW Current CLK / CLK CLK / CLK (VTCLK/VTCLK Open) (VTCLK/VTCLK Open) mV mV mV mV mA mA W W mW/C
Internal Input Termination Resistor Internal Output Termination Resistor Internal I/O Termination Resistor Temperature Coefficient
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. 6. CML outputs require 50 W receiver termination resistors to VCC for proper operation. 7. Vth is applied to the complementary input when operating in single-ended mode. 8. VCMR min varies 1:1 with VEE, VCMR max varies 1:1 with VCC.
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NB7L11M
Table 5. AC CHARACTERISTICS (VCC = 2.375 V to 3.465 V, VEE = 0 V; Note 9)
Symbol Characteristic Min VOUTPP Output Voltage Amplitude (@VINPPmin) fin 6 GHz (See Figure 3) fin 8 GHz Maximum Operating Data Rate Propagation Delay to Output Differential Duty Cycle Skew (Note 10) Within-Device Skew Device-to-Device Skew (Note 11) RMS Random Clock Jitter (Note 12) fin = 6 GHz fin =8 GHz Peak/Peak Data Dependent Jitter fin = 2.488 Gb/s (Note 13) fdata =5 Gb/s fdata =10 Gb/s Input Voltage Swing/Sensitivity (Differential Configuration) (Note 14) Output Rise/Fall Times @ 1 GHz Q, Q (20% - 80%) 75 280 140 10 70 -40C Typ 400 300 12 110 2.0 3.0 20 0.2 0.2 2.0 3.0 5.0 150 5.0 15 50 0.5 0.5 5.0 8.0 10 Max Min 280 140 10 70 25C Typ 400 300 12 110 2.0 3.0 20 0.2 0.2 2.0 3.0 5.0 150 5.0 15 50 0.5 0.5 5.0 8.0 10 Max Min 280 140 10 70 85C Typ 400 300 12 110 2.0 3.0 20 0.2 0.2 2.0 3.0 5.0 150 5.0 15 50 0.5 0.5 5.0 8.0 10 Max mV Unit
fdata tPLH, tPHL tSKEW
Gb/s ps ps
tJITTER
ps
VINPP tr tf
400 30
2500 60
75
400 30
2500 60
75
400 30
2500 60
mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Measured by forcing VINPP (TYP) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps (20% - 80%). 10. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+ @1 GHz. 11. Device to device skew is measured between outputs under identical transition @ 1 GHz. 12. Additive RMS jitter with 50% duty cycle clock signal at 8 GHz & 10 GHz. 13. Additive peak-to-peak data dependent jitter with input NRZ data at PRBS 2^23-1. 14. VINPP (MAX) cannot exceed VCC - VEE. Input voltage swing is a single-ended measurement operating in differential mode.
500 OUTPUT VOLTAGE AMPLITUDE (mV) VCC = 3.3 V VCC = 2.5 V 300
400
200
100
0
0
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) at Ambient Temperature (Typical) (VINPP = 400 mV)
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NB7L11M
Voltage (50 mV/div)
Voltage (50 mV/div)
DDJ = 1 ps*
DDJ = 1.2 ps**
Time (80.4 ps/div)
Time (40 ps/div)
Figure 4. Typical Output Waveform at 2.488 Gb/s with PRBS 2^23-1 (Vinpp = 75 mV)
*Input signal DDJ = 6.4 ps
Figure 5. Typical Output Waveform at 5 Gb/s with PRBS 2^23-1 (Vinpp = 75 mV)
**Input signal DDJ = 7.2 ps
Voltage (50 mV/div)
DDJ = 2 ps***
Voltage (50 mV/div)
DDJ = 2 ps***
Time (18.6 ps/div)
Time (18.2 ps/div)
Figure 6. Typical Output Waveform at 10.7 Gb/s with PRBS 2^23-1 (Vinpp = 75 mV)
***Input signal DDJ = 11 ps
Figure 7. Typical Output Waveform at 12 Gb/s with PRBS 2^23-1 (Vinpp = 75 mV)
***Input signal DDJ = 13 ps
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NB7L11M
CLK VINPP = VIH(CLK) - VIL(CLK) CLK Q Q tPLH VOUTPP = VOH(Q) - VOL(Q) tPHL
Figure 8. AC Reference Measurement
NB7L11M
VCC
VCC
Receiver Device
50 W Q
50 W
50 W
50 W CLK
Z = 50 W Q Z = 50 W CLK
Figure 9. Typical Termination for Output Driver Using External Termination Resistor (Refer to Application Notes AND8020/D and AND8173/D)
CLK Vth Vth CLK
CLK
CLK
Figure 10. Differential Input Driven Single-Ended
Figure 11. Differential Inputs Driven Differentially
VCC Vthmax
VIHmax VILmax CLK VIH Vth VIL VIHmin VILmin
VCC VCMmax CLK VCMR CLK VCMmax GND
VIHCLKmax VILCLKmax V(CLK) = VIHCLK - VILCLK VIHCLKtyp VILCLKtyp VIHCLKmin VILCLKmin
Vth
Vthmin GND
Figure 12. Vth Diagram
Figure 13. VCMR Diagram
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NB7L11M
VCC
50 W
50 W Q Q
16 mA VEE
Figure 14. CML Output Structure
Table 6. INTERFACING OPTIONS
INTERFACING OPTIONS CML LVDS AC-COUPLED RSECL, LVPECL LVTTL, LVCMOS CONNECTIONS Connect VTCLK, VTCLK to VCC Connect VTCLK, VTCLK together CLK input Bias VTCLK, VTCLK Inputs within (VCMR) Common Mode Range Standard ECL Termination Techniques. See AND8020/D. An external voltage should be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL and VCC/2 for LVCMOS inputs.
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NB7L11M
Application Information
All NB7L11M inputs can accept PECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential input signal (LVDS, PECL, or CML) are
VCC
minimum input swing of 75 mV and the maximum input swing of 2500 mV. Within these conditions, the input voltage can range from VCC to 1.2 V. Examples interfaces are illustrated below in a 50 W environment (Z = 50 W).
VCC
50 W
50 W
Q
Z VCC VCC Z
CLK VTCLK VTCLK CLK VEE 50 W 50 W NB7L11M
CML Driver
Q VEE
Figure 15. CML to CML Interface
VCC
VCC
50 W PECL Driver Recommended RT Values VCC RT RT VEE VEE 5.0 V 290 W 3.3 V 150 W 2.5 V 80 W 50 W RT
Z VBias VBias Z
CLK VTCLK VTCLK CLK 50 W NB7L11M 50 W
VEE
Figure 16. PECL to CML Receiver Interface
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NB7L11M
VCC VCC
Z LVDS Driver Z
CLK VTCLK VTCLK CLK 50 W NB7L11M 50 W
VEE
VEE
Figure 17. LVDS to CML Receiver Interface
VCC
VCC
Z LVTTL/ LVCMOS Driver No Connect* No Connect VREF
CLK VTCLK 50 W NB7L11M VTCLK CLK 50 W Recommended VREF Values VREF LVCMOS VCC - VEE 2 LVTTL 1.5 V
VEE
*or 60 pF to GND
VCC
Figure 18. LVCMOS/LVTTL to CML Receiver Interface ORDERING INFORMATION
Device NB7L11MMN NB7L11MMNG NB7L11MMNR2 NB7L11MMNR2G Package QFN-16 QFN-16 (Pb-Free) QFN-16 QFN-16 (Pb-Free) Shipping 123 Units/Rail 123 Units/Rail 3000 Tape & Reel 3000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB7L11M
PACKAGE DIMENSIONS
16 PIN QFN MN SUFFIX CASE 485G-01 ISSUE B
D A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG DIM A A1 A3 b D D2 E E2 e K L SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 --- 0.30 0.50
PIN 1 LOCATION
0.15 C 0.15 C
0.10 C
16 X
0.08 C
16X
L
NOTE 5 4
16X
K
1 16 16X 13
0.10 C A B 0.05 C
NOTE 3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
CCC CCC CCC
TOP VIEW (A3) SIDE VIEW D2
5
E
A A1
C
e
8
EXPOSED PAD
9
E2
12
e
b BOTTOM VIEW
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NB7L11M/D

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